Integrated transmission circuit and method

ABSTRACT

An integrated transmission circuit and method for transmitting output data to a chipset via a transmission interface are provided. The integrated transmission circuit includes a first application circuit, a second application circuit, a media access control (MAC) circuit, and a physical layer (PHY) circuit. The first application circuit is used for receiving and processing first data to output first processed data. The second application circuit is used for receiving and processing second data to output second processed data. The MAC circuit is coupled to the first application circuit and the second application circuit, and used for encoding the first processed data and the second processed data so as to output encoded data. The PHY circuit is coupled to the MAC circuit to receive the encoded data so as to output the output data to the transmission interface.

CROSS-REFERENCES TO RELATED APPLICATIONS

This non-provisional application claims priority under 35 U.S.C. §119(a)on Patent Application No. 97136373 filed in Taiwan, R.O.C. on Sep. 22,2008, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Technical Field

The disclosure relates to an integrated transmission circuit and method,and more particularly, to an integrated transmission circuit and methodfor integrating a plurality of application circuits into a chip.

2. Related Art

A Peripheral Component Interconnect Express (PCI Express) is a maturehigh-speed transmission interface, and has the advantages of low powerconsumption, high transmission performance, and low pin count.

Currently, most commercially available computer systems (for example,notebook computers or desktop computers), support the PCI Expressinterfaces. A variety of application circuits such as a 10/100 MbitEthernet chip and a Gigabit Ethernet chips may be connected to a chipsetof a computer system via PCI Express interfaces. However, in the currentstate of the art, each application circuit is designed with an exclusivePCI Express interface for connection to the chipset, and the chipsetaccordingly needs to be designed with a plurality of PCI Expressinterfaces in consideration of the number of application circuits in aproduct for coupling the chipset to different application circuits. As aresult, the design cost of the chipset is increased. Moreover, if thenumber of PCI Express ports increases, the size of a computermotherboard must be increased, which is in opposition to the industryaim of lightness and thinness.

SUMMARY

Accordingly, the disclosure is directed to an integrated transmissioncircuit and method. Through the circuit or method of the disclosure, thenumber of PCI Express ports to be used is reduced, and the size of acomputer motherboard is reduced.

The disclosure provides an integrated transmission circuit fortransmitting output data via a transmission interface. The integratedtransmission circuit includes a first application circuit, a secondapplication circuit, a media access control (MAC) circuit, and aphysical layer (PHY) circuit. The first application circuit is used forreceiving and processing first data to output first processed data. Thesecond application circuit is used for receiving and processing seconddata to output second processed data. The MAC circuit is coupled to thefirst application circuit and the second application circuit, and usedfor encoding the first processed data and the second processed data, soas to output encoded data. The PHY circuit is coupled to the MAC circuitto receive the encoded data so as to output the output data to thetransmission interface. The MAC circuit interactively encodes the firstprocessed data and the second processed data, so as to output theencoded data to the PHY circuit.

The disclosure also provides an integrated transmission method fortransmitting output data via a transmission interface. The integratedtransmission method includes: receiving and processing first data tooutput first processed data; receiving and processing second data tooutput second processed data; providing an MAC circuit to interactivelyencode the first processed data and the second processed data so as tooutput encoded data; and coupling a PHY circuit to the MAC circuit toreceive the encoded data so as to output the output data to thetransmission interface.

Preferred embodiments and effects of the disclosure are illustratedbelow with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure will become more fully understood from the detaileddescription given herein below for illustration only, and thus are notlimitative of the disclosure, wherein:

FIG. 1 is a schematic view of an integrated transmission circuitaccording to a first embodiment of the disclosure;

FIG. 2 is a schematic view of an integrated transmission circuitaccording to a second embodiment of the disclosure;

FIG. 3 is a schematic view of an integrated transmission circuitaccording to a third embodiment of the disclosure;

FIG. 4 is a schematic view of an integrated transmission circuitaccording to a fourth embodiment of the disclosure; and

FIG. 5 is a flow chart of an integrated transmission method according tothe disclosure.

DETAILED DESCRIPTION

FIG. 1 is a schematic view of an integrated transmission circuitaccording to a first embodiment of the disclosure. Please refer to FIG.1, an integrated transmission circuit 1 of the disclosure is used fortransmitting output data via a transmission interface 50, and includes afirst application circuit 10, a second application circuit 20, an MACcircuit 30, and a PHY circuit 40.

The first application circuit 10 is used for receiving and processingfirst data Si1 to output first processed data Sp1. The secondapplication circuit 20 is used for receiving and processing second dataSi2 to output second processed data Sp2. In an embodiment, the firstapplication circuit 10 is a card reader, and the second applicationcircuit 20 is a 10M/100M/Gigabit Ethernet controller. Alternatively, thefirst application circuit 10 is an Ethernet controller, and the secondapplication circuit 20 is a wireless local area network (WLAN)controller. It should be noted that the first application circuit 10 andthe second application circuit 20 have different functions.

The MAC circuit 30 is coupled to the first application circuit 10 andthe second application circuit 20, and used for encoding the firstprocessed data Sp1 and the second processed data Sp2 so as to outputencoded data Se. The PHY circuit 40 is coupled to the MAC circuit 30 toreceive the encoded data Se so as to output the output data Sout to thetransmission interface 50. According to an embodiment, the transmissioninterface 50 is a PCI Express interface. The PHY circuit 40 transmitsthe output data Sout to a chipset 60 via the transmission interface 50.For the convenience of illustration, the following embodiments aredescribed by taking the PCI Express interface as an example of thetransmission interface 50; however, the disclosure is not limited tothis, and the data may also be transmitted via other types oftransmission interfaces.

As shown in FIG. 1, the disclosure discloses a technique that aplurality of application circuits having different functions shares thesame MAC circuit 30 and the same PHY circuit 40, so as to reduce thenumber of interfaces to be used. Moreover, in the disclosure applicationcircuits sharing the PCI Express interface are integrated into the samecontrol chip based on the definition that the PCI Express interfacespecifications can support a plurality of functions at the same time,that is, the first application circuit 10 and the second applicationcircuit 20 are disposed in the same chip. As such, as compared with theconventional approach that each application circuit needs an MAC circuitand a PHY circuit for PCI Express, the area required by circuit layoutor integrated circuit (IC) design is saved by sharing the MAC circuit 30and the PHY circuit 40 through integration.

Furthermore, the upper-layer chipset 60 is notified during the deviceconfiguration of a PCI Express protocol that the device (i.e., the chipintegrated with the first application circuit 10 and the secondapplication circuit 20), has a plurality of functions. As such,different application circuits are integrated into the same controlchip, and only one PCI Express port is used, so that the number of PCIExpress ports to be used is reduced significantly.

In addition, according to an embodiment of the disclosure, in order totransmit the first processed data Sp1 and the second processed data Sp2to the chipset smoothly, the MAC circuit 30 interactively encodes thefirst processed data Sp1 and the second processed data Sp2 so as tooutput the encoded data Se in compliance with PCI Expressspecifications, to the PHY circuit 40. For example, if the firstapplication circuit 10 is a card reader and the second applicationcircuit 20 is an Ethernet controller, the first processed data Sp1 ismemory card access data, and the second processed data Sp2 is networktransmission data. As the first application circuit 10 and the secondapplication circuit 20 share the MAC circuit 30 and the PHY circuit 40in the disclosure, the MAC circuit 30 and the PHY circuit 40 need toprocess the memory card access data and the network transmission data.After the upper-layer chipset 60 arranges a work schedule, the MACcircuit 30 will encode the memory card access data in a first timecycle, encode the network transmission data in a second time cycle, andtransmit the encoded data Se to the PHY circuit 40. Next, the encodeddata Se is converted by the PHY circuit 40 into an output signal thatcomplies with the PCI Express interface, and then transmitted to thechipset 60. As such, the chipset 60 may receive the output dataincluding the memory card access data and the network transmission data,and perform corresponding processing. In addition, it should be notedthat in order to enable the MAC circuit 30 to interactively process thememory card access data and the network transmission data, according toan embodiment, an arbiter or a multiplexer may be disposed between theMAC circuit 30 and the application circuits (10 and 20), to output thememory card access data or the network transmission data to the MACcircuit 30 selectively.

Moreover, the integrated transmission circuit of the disclosure may alsoturn off power supplies of the application circuits according to theservice condition of the circuit, so as to achieve power saving. Forexample, it is assumed that the first application circuit 10 is WLANchip, and the second application circuit 20 is an Ethernet controller.When a user uses the WLAN chip to access a network, the firstapplication circuit 10 is enabled, and the second application circuit 20may turn off (or disable), a power supply thereof, for example, a PHYpower supply in the second application circuit 20 is turned off, orclock signals are turned off, so as to achieve power management andpower saving. It should be understood that the combination of the firstapplication circuit 10 and the second application circuit 20 of thedisclosure is not limited to the above description, and the applicationcircuits may also be a combination of a display control chip, a DVDcontrol chip, a sound effect control chip, a web cam control chip, orthe like.

FIG. 2 is a schematic view of an integrated transmission circuitaccording to a second embodiment of the disclosure. In the secondembodiment, in order to cooperate with the coupled first applicationcircuit 10 and second application circuit 20 the MAC circuit 30 mayinclude a first buffer 32 and a second buffer 34. The first buffer 32 isused for buffering the first processed data Sp1 output by the firstapplication circuit 10, and the second buffer 34 is used for bufferingthe second processed data Sp2 output by the second application circuit2. The MAC circuit 30 may use the first buffer 32 to read the firstprocessed data Sp1 so as to encode the first processed data Sp1, and usethe second buffer 34 to read the second processed data Sp2 so as toencode the second processed data Sp2, respectively. Moreover, if the MACcircuit 30 is coupled to more than two application circuits, the numberof buffers to be disposed is increased according to the number of theapplication circuits. For example, if a third application circuit and afourth application circuit are additionally provided and coupled to theMAC circuit 30, the MAC circuit 30 may further include a third bufferand a fourth buffer, and so on.

FIG. 3 is a schematic view of an integrated transmission circuitaccording to a third embodiment of the disclosure. In the thirdembodiment, a case involving more than two application circuits isillustrated. In the third embodiment, the integrated transmissioncircuit further includes a third application circuit 70. The thirdapplication circuit 70 is used for receiving and processing third dataSi3 to output third processed data Sp3. The MAC circuit 30 is furthercoupled to the third application circuit 70, and interactively encodesthe first processed data Sp1, the second processed data Sp2, and thethird processed data Sp3 so as to output the encoded data Se to the PHYcircuit 40. The first application circuit 10 is a card reader, thesecond application circuit 20 is a network controller, and the thirdapplication circuit 70 is a display controller. It is observable fromthe third embodiment that a plurality of application circuits isintegrated into the same chip to share the MAC circuit 30 and the PHYcircuit 40 through the integrated transmission circuit of thedisclosure, and only one PCI Express port is used and coupled to thechipset.

FIG. 4 is a schematic view of an integrated transmission circuitaccording to a fourth embodiment of the disclosure. The fourthembodiment is illustrated by taking a computer system architecture as anexample, wherein the computer system has a central processing unit (CPU)80. As shown in the figure, a chipset 60 has three PCI Express ports61-63. In this embodiment, the PCI Express chipset 60 is a so-calledroot complex. An integrated transmission circuit 1 of the disclosurewill integrate a first application circuit 10, a second applicationcircuit 20, and a third application circuit 70, which are assumed to bea card reader, a network controller, and a display controller,respectively. In a computer system (for example, a notebook computer),the first application circuit 10 is a built-in card reader control chipfor coupling to memory cards of different formats; the secondapplication circuit 20 is a built-in network controller (an Ethernetchip and/or 802.11 WLAN chip), for coupling to a network line orreceiving WLAN data; and the third application circuit 70 is a displaycontroller for coupling to a display to generate an image controlsignal.

It is observable from FIG. 4 that a plurality of application circuitshaving different functions is integrated to share the MAC circuit 30 andthe PHY circuit 40 through the integrated transmission circuit 1 of thedisclosure, and only one PCI Express port 61 is used. Output data istransmitted to the chipset 60 via a PCI Express interface 50, and thentransmitted by the chipset 60 to the CPU 80 in the upper layer; and theCPU 80 processes related data of the application circuits so as toenable the application circuits to operate normally.

FIG. 5 is a flow chart of an integrated transmission method according tothe disclosure. The integrated transmission method of the disclosure isused for transmitting output data via a transmission interface, andincludes the following steps:

In Step S10, first data is received and processed to output firstprocessed data.

In Step S20, second data is received and processed to output secondprocessed data.

In Step S30, an MAC circuit is provided to interactively encode thefirst processed data and the second processed data so as to outputencoded data.

In Step S40, a PHY circuit is coupled to the MAC circuit to receive theencoded data so as to output the output data to the transmissioninterface.

In the Step S10, according to an embodiment, the first processed data isgenerated by a card reader, and the second processed data is generatedby an Ethernet controller. Alternatively, the first processed data isgenerated by an Ethernet controller, and the second processed data isgenerated by a WLAN controller. Moreover, in the disclosure, the firstprocessed data and the second processed data are generated by the samechip.

In the Step S30, according to an embodiment, the MAC circuit furtherincludes: a first buffer, for buffering the first processed data; and asecond buffer, for buffering the second processed data. The MAC circuitmay use the first buffer to read the first processed data so as toencode the first processed data, and use the second buffer to read thesecond processed data so as to encode the second processed data. Theoutput encoded data complies with specifications of the transmissioninterface, and if the transmission interface is a PCI Express interface,the encoded data output by the MAC circuit complies with PCI Expressinterface specifications.

In addition to the above steps, the method may further include:receiving and processing third data to output third processed data; andinteractively encoding, by the MAC circuit, the first processed data,the second processed data, and the third processed data so as to outputthe encoded data. The first processed data is generated by a cardreader, the second processed data is generated by a network controller,and the third processed data is generated by a display controller.Moreover, if the first data does not need to be processed, theintegrated transmission method of the disclosure may further includeceasing to receive the first data and ceasing to process the first data,so as to achieve a power saving.

To sum up, the disclosure provides an integrated transmission circuit,which includes different types of application circuits, such as the cardreader, the 10M/100M/Gigabit Ethernet controller, the WLAN controller,the display control chip, the DVD control chip, and the web cam controlchip. The application circuits share the same MAC circuit and the samePHY circuit to transmit data to a chipset of a computer system. Thisbeing the case, the area required by circuit layout or IC design isreduced. Moreover, the integrated transmission circuit of the disclosurealso has a power management function; such that when an applicationcircuit does not need to be used the power supply thereof is turned off,so as to reduce power consumption.

The technical content of the disclosure has been disclosed throughpreferred embodiments, but is not intended to be limited thereto.Various variations and modifications made by those skilled in the artwithout departing from the spirit of the disclosure fall within thescope of the disclosure as defined by the appended claims.

1. An integrated transmission circuit, for transmitting output data viaa transmission interface, the integrated transmission circuitcomprising: a first application circuit, for receiving and processingfirst data to output first processed data; a second application circuit,for receiving and processing second data to output second processeddata; a media access control (MAC) circuit, coupled to the firstapplication circuit and the second application circuit, for encoding thefirst processed data and the second processed data so as to outputencoded data; and a physical layer (PHY) circuit, coupled to the MACcircuit to receive the encoded data so as to output the output data tothe transmission interface; wherein the first application circuit andthe second application circuit have different functions; and the MACcircuit interactively encodes the first processed data and the secondprocessed data so as to output the encoded data to the PHY circuit. 2.The integrated transmission circuit according to claim 1, wherein thefirst application circuit is a card reader, and the second applicationcircuit is an Ethernet controller.
 3. The integrated transmissioncircuit according to claim 1, wherein the first application circuit isan Ethernet controller, and the second application circuit is a wirelesslocal area network (WLAN) controller.
 4. The integrated transmissioncircuit according to claim 1, wherein when the first application circuitis not used, the first application circuit is disabled.
 5. Theintegrated transmission circuit according to claim 1, furthercomprising: a third application circuit, for receiving and processingthird data to output third processed data; wherein the MAC circuit isfurther coupled to the third application circuit, and interactivelyencodes the first processed data, the second processed data, and thethird processed data to so as output the encoded data to the PHYcircuit.
 6. The integrated transmission circuit according to claim 5,wherein the first application circuit is a card reader, the secondapplication circuit is a network controller, and the third applicationcircuit is a display controller.
 7. The integrated transmission circuitaccording to claim 1, wherein the first application circuit and thesecond application circuit are disposed in a same chip.
 8. Theintegrated transmission circuit according to claim 1, wherein the MACcircuit comprises: a first buffer, for buffering the first processeddata; and a second buffer, for buffering the second processed data;wherein the MAC circuit uses the first buffer to read the firstprocessed data so as to encode the first processed data, and the MACcircuit uses the second buffer to read the second processed data so asto encode the second processed data.
 9. The integrated transmissioncircuit according to claim 1, wherein the transmission interface is aPeripheral Component Interconnect Express (PCI Express) interface. 10.The integrated transmission circuit according to claim 1, wherein thePHY circuit transmits the output data to a chipset via the transmissioninterface.
 11. An integrated transmission method, for transmittingoutput data via a transmission interface, the integrated transmissionmethod comprising: receiving and processing first data to output firstprocessed data; receiving and processing second data to output secondprocessed data; providing a media access control (MAC) circuit tointeractively encode the first processed data and the second processeddata so as to output encoded data; and coupling a physical layer (PHY)circuit to the MAC circuit to receive the encoded data so as to outputthe output data to the transmission interface;
 12. The integratedtransmission method according to claim 11, wherein the first processeddata is generated by a card reader, and the second processed data isgenerated by an Ethernet controller.
 13. The integrated transmissionmethod according to claim 11, wherein the first processed data isgenerated by an Ethernet controller and the second processed data isgenerated by a wireless local area network (WLAN) controller.
 14. Theintegrated transmission method according to claim 11, furthercomprising: ceasing to receive the first data and ceasing to process thefirst data.
 15. The integrated transmission method according to claim11, further comprising: receiving and processing third data to outputthird processed data; and interactively encoding, by means of the MACcircuit, the first processed data, the second processed data, and thethird processed data so as to output the encoded data.
 16. Theintegrated transmission method according to claim 15, wherein the firstprocessed data is generated by a card reader, the second processed datais generated by a network controller, and the third processed data isgenerated by a display controller.
 17. The integrated transmissionmethod according to claim 11, wherein the first processed data and thesecond processed data are generated by the same chip.
 18. The integratedtransmission method according to claim 11, wherein the MAC circuitcomprises: a first buffer, for buffering the first processed data; and asecond buffer, for buffering the second processed data; wherein the MACcircuit uses the first buffer to read the first processed data so as toencode the first processed data, and the MAC circuit uses the secondbuffer to read the second processed data so as to encode the secondprocessed data.
 19. The integrated transmission method according toclaim 11, wherein the transmission interface is a Peripheral ComponentInterconnect Express (PCI Express) interface.
 20. The integratedtransmission method according to claim 11, wherein the PHY circuittransmits the output data to a chipset via the transmission interface.